EDAPS



EDAPS




EDAPS


EDAPS



EDAPS



EDAPS



EDAPS



EDAPS




EDAPS


EDAPS


EDAPS


EDAPS



EDAPS


EDAPS


EDAPS



EDAPS

EPS



EDAPS 2018 Tutorials

Tutorial-1: Jitter Modeling and Analysis

Speaker-1:
Ramachandra Achar - Power Integrity Fundamentals and PSIJ analysis


Speaker-2:
Jun Fan - Statistical analysis of HBM channel performance

Speaker-3:
Paul Franzon - Chip to Chip Signaling in High Speed Interconnects

Tutorial-2: Machine Learning in Hardware Design

Speaker-1:
Flavio Canavero - Application of SVM for Design Optimization of High-Speed Links


Speaker-2:
Dries Vande Ginste - Machine Learning based Generative Stochastic Modeling of High-Speed Interconnects

Speaker-3:
Tom Dhaene - Challenges in the optimization of modern RF and EM systems: a Bayesian perspective

Tutorial-3: DDR5 Design

Speaker-1:
Ramaswamy Parthasarathy - DDR Memory Technologies: A System Designer Perspective


Speaker-2:
Sung Joo Park - DDR5: SI/PI Challenges and Considerations


Speaker-3:
Kumar Keshavan - Design Space Constraint Generation Using Machine Learning for DDR4/DDR5 Memory Systems

Tutorial-4: Power Delivery Network Design and Modeling

Speaker-1:
Anurag Bhargava - How to Design for Power Integrity


Speaker-2:
Arun Chandrasekhar - Power Delivery Techniques for High Performance Processors