Directions and Opportunities in Advanced Packaging Technology
Ravi Mahajan is an Intel Fellow and the Co-director of Pathfinding and Assembly and Packaging technologies for 7nm silicon and beyond in the Technology and Manufacturing Group at Intel Corporation. He is responsible for planning and carrying out multi-chip package pathfinding programs for the latest Intel process technologies. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. Ravi has led efforts to define and set strategic direction for package architecture, technologies and assembly processes at Intel since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Earlier in his Intel career, he spent five years as group manager for thermal mechanical tools and analysis. In that role, Ravi oversaw a Thermal-Mechanical Lab chartered with delivering detailed thermal and mechanical characterization of Intel's packaging solutions for current and future processors.
A prolific inventor and recognized expert in microelectronics packaging technologies, Ravi holds more than 40 patents, including the original patent for a silicon bridge that became the foundation for Intel's Embedded Multi-Die Interconnect Bridge technology. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 30 papers on topics related to his area of expertise.
Ravi joined Intel in 1992 after earning a bachelor's degree from Bombay University, a master's degree from the University of Houston, and a Ph.D. from Lehigh University, all in mechanical engineering. His contributions during his Intel career have earned him numerous industry honors, including the SRC's 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI award from SEMITHERM and the 2016 Allan Kraus Thermal Management Medal from the American Society of Mechanical Engineers. He has been nominated as an IEEE CPMT Distinguished Lecturer. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. Additionally he has been long associated with ASME's InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. He was named an Intel Fellow in 2017.