Return2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Chandigarh, India - December 16-18, 2018 - Preliminary Program

Preliminary Program

Sunday, December 16, 2018 Monday, December 17, 2018 Tuesday, December 18, 2018
EDAPS TUTORIALS
Tutorial 1 - Jitter Modeling and Analysis
Chair:
Raj Kumar Nagpal, Synopsys

9:00 - 10:00
  • Power Integrity Fundamentals and PSIJ analysis
    Ramachandra Achar
    Carleton University
10:00 - 11:00
  • Statistical analysis of HBM channel performance
    Chulsoon Hwang
    MST
11:00 - 11:30
Tea/Coffee Break

11:30 - 12:30
  • Chip to Chip Signaling in High Speed Interconnects
    Paul Franzon
    NCSU
Tutorial 2 - DDR5 Design
Chair:
Rohit Sharma, IITR

9:00 - 10:00
  • DDR Memory Technologies: A System Designer Perspective
    Ramaswamy Parthasarathy, Vishram S Pandit
    Intel
10:00 - 11:00
  • DDR5: SI/PI Challenges and Considerations
    Sung Joo Park
    Samsung
11:00 - 11:30
Tea/Coffee Break

11:30 - 12:30
  • Design Space Constraint Generation Using Machine Learning for DDR4/DDR5 Memory Systems
    Kumar Keshavan
    Cadence

12:30 - 1:30
Lunch Break

Tutorial 3 - Machine Learning in Hardware Design
Chair:
Jai Narayan Tripathi, ST Microelectronics

1:30 - 2:30
  • Application of SVM for Design Optimization of High-Speed Links
    Flavio Canavero
    Politecnico di Torino
2:30 - 3:30
  • Machine Learning based Generative Stochastic Modeling of High-Speed Interconnects
    Dries Vande Ginste
    Ghent University
3:30 - 4:00
Tea/Coffee Break

4:00 - 5:00
  • Challenges in the optimization of modern RF and EM systems: a Bayesian perspective
    Tom Dhaene
    Ghent University
Tutorial 4 - Power Delivery Network Design and Modeling
Chair:
Rakesh Malik, Vervesemi

1:30 - 3:30
  • How to Design for Power Integrity
    Anurag Bhargava
    Keysight Technologies
3:30 - 4:00
Tea/Coffee Break

4:00 - 5:00
  • Power Delivery Techniques for High Performance Processors
    Arun Chandrasekhar
    Intel

6:00 - 8:00
Welcome Reception

7:30 - 8:30 am
Registration

8:30 - 10:00
Plenary Session 1
Chairs:
Rohit Sharma, IIT Ropar
Raj Kumar Nagpal, Synopsys
  • Directions and Opportunities in Advanced Packaging Technology
    Ram Viswanath
    Intel
  • Electronics Packaging: MEMS Pressure Transducers for Aerospace application - A case study
    M. Manjunatha Nayak
    IISc, Bangalore

10:00 - 10:20
Tea/Coffee Break

10:20 - 12:00
Session 1: ICs, Interposers and Systems
Chairs:
Jai Narayan Tripathi, ST Microelectronics
Jose Schutt-Aine, University of Illinois
  • M-I.1. Heterogeneous SoC Integration with EMIB [121]
    Ram Viswanath, Arun Chandrasekhar, Sriram Srinivasan, Zhiguo Qian, Ravi Mahajan
    Intel
  • M-I.2. Modeling of Through-silicon Via (TSV) with an Emdedded High-density Metal-insulator-metal (MIM) Capacitor [35]
    Kyunjun Cho, Youngwoo Kim, Subin Kim, Gapyeol Park, Kyungjune Son, Hyunwook Park, Seongguk Kim, Sumin Choi, Dong-Hyun Kim and Joungho Kim
    KAIST
  • M-I.3. On-chip Reference-less Clock Jitter Measurement [106]
    Ankur Bal, Rupesh Singh
    STMicroelectronics
  • M-I.4. Calculations of Temperature Distributions for Power MMICs in 3-D Packages[32]
    Xing Yan, Chengrui Zhang, Liang Zhou
    Shanghai Jiaotong University
  • M-I.5. CLOCK PSIJ Study under different PDN choices in LPDDR3 systems [139]
    Vijay Kumar Singh, Raj Kumar Nagpal, Dinesh Kumar Sharma, Luis Simoes, Eduard Kulchinsky
    Synopsys Inc.

12:00 - 1:30
Lunch Break

1:30 - 3:10
Session 2: Machine Learning for System Integration
Chairs:
Flavio Canavero, Politecnico di Torino
Erping Li, Zhejiang University
  • M-II.1. Predition of IC Equivalent Magnetic Dipoles Using Deep Convolutional Neural Network [188]
    Hanzhi Ma, Erping Li
    Zhejiang University
  • M-II.2. Efficiency of the Perturbative Stochastic Galerkin Method for Multiple Differential PCB Lines [201]
    Xinglong Wu*, Flavia Grassi*, Paolo Manfredi+, Dries Vande Ginste **
    *Politecnico di Milano, Italy,
    +Politecnico di Torino, Italy,
    **Ghent University/imec, Belgium
  • M-II.3. Wafer Quality Inspection using Memristive LSTM, ANN, DNN and HTM [140]
    Kazybek Adam, Kamilya Smagulova, Olga Krestinskaya, Alex Pappachen James
    Nazarbayev University
  • M-II.4. Machine Learning for Fast Characterization of Magnetic Logic Devices [62]
    Arun Kaintura *, Kyle Foss*, Ivo Couckuyt*, Tom Dhaene*, Odysseas Zografos+, Adrien Vaysset+, Bart Soree+
    *Ghent University,
    +IMEC
  • M-II.5. Preliminary Application of Deep Learning to Design Space Exploration [210]
    Kallol Roy, Hakki Torun Mert, Madhavan Swaminathan
    Georgia Institute of Technology

3:10 - 3:25 pm
Tea/Coffee Break

3:25 - 5:05 pm
Session 3 - Modeling and Simulation
Chairs:
Dipanjan Gope, IISc
Bhyrav Mutnury, Dell
  • M-III.1. Contemporary On-chip System Modeling using FDTD in Low Power Regime [193]
    Yash Agrawal*, Rajeevan Chandel+, Mekala Girish**, Rutu Parekh*
    *Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, Gujarat, India,
    +National Institute of Technology, Hamirpur, Himachal Pradesh, India,
    **Vidya Jyoti Institute of Technology, Hyderabad, Telangana, India
  • M-III.2. Signal and Power Integrity Analysis of DDR4 Address Bus of Onboard Memory Module [85]
    Anil Kumar Pandey
    Keysight Technologies
  • M-III.3. Crosstalk Analysis for Rough Copper Interconnects in Ternary Logic [126]
    Sunil Pathania*, Somesh Kumar+, Rohit Sharma*
    *Indian Institute of Technology Ropar,
    +Indian Institute of Information Technology Nagpu
  • M-III.4. Rational Function Approximation of Parallel Coupled line Interconnects in RF Applications [98]
    Vrinda K, N. S. Murty, Dhanesh G. Kurup
    Amrita University
  • M-III.5. LIM Algorithms for Diodes and Branch Capacitors [91]
    Jose Schutt-Aine*, Patrick Goh+
    *University of Illinois, +Universiti Sains Malaysia

5:05 - 5:30
Break

5:30 - 7:00 pm
Session 4 - Poster/Interactive Session
Chairs:
Suresh Subramanyam, Intel
Hitesh Shrimali, IITM
  • P-I.1. Design of Ultra wide band Monopole Antenna with Band rejection Capability Using Minkowski Fractal Curve [109]
    Balaka Biswas*, Ayan Karmakar+
    *CSIO-CSIR, Chandigarh,
    +SCL,Chandigarh
  • P-I.2. Study of Series-series Topology for Suppressing Electromagnetic Interference (EMI) for Digital TV Wireless Power Transfer (WPT) Systems [213]
    Mumpy Das, Seungtaek Jeong , Boogyo Sim , Seongsoo Lee, Seokwoo Hong, Youngwoo Kim, Joungho Kim
    KAIST
  • P-I.3. A Methodology for distributed Co-design and Co-extraction of Die Re-distribution Layer and Package [159]
    Ashish Gupta, Abhishek Bhattacharya, Vansh Mohan, Ayush Singh, Ritabrata Bhattacharya and Vikas Aggarwal
    Cadence Design System
  • P-I.4. Power Supply Noise Coupling Mitigation across High Speed Serial Links [53]
    Manjunath J, Mukesh Moorthy
    INTEL
  • P-I.5. Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices [150]
    Aidana Irmanova, Grant Ellis, Alex Pappachen James
    Nazarbayev University
  • P-I.6. Impact of Via Stub Position on High Speed Serial Links [181]
    Vijendera Kumar, Sukumar Muthusamy, Sanjay Kumar, Mallikarjun Vasa, Gowri Anand, Bhyrav Mutnury
    DELL EMC
  • P-I.7. Optimized Package Routing for Power Pin Current Balance [43]
    Weixia Liang, Wei Shen, Srikrishnan Venkataraman, Puneesh Puri
    Intel Corporation
  • P-I.8. A New Compact Dual-Polarized Integrated Antenna Array for 2G/3G/4G/LTE Base Station Applications [8]
    Huashan Luan, Hong-Li Peng, Jun-Fa Mao
    Shanghai Jiao Tong University
  • P-I.9. Power Delivery Network Design Strategy for Next Generation High Speed IO [102]
    Mukesh Moorthy, Manjunath J
    Intel Technology India Pvt Ltd
  • P-I.10. Phase Change Material Compact Model: Validation and Sensitivity as Thermal Interface Material [180]
    Javed Shaikh*, Je-Young Chang+, Weihua Tang+
    *Intel Corporation, Bangalore,
    +Intel Corporation, Chandler, AZ, USA
  • P-I.11. PDN design and sensitivity analysis using synthesized models in DDR SI/PI co-simulations [87]
    Javid Mohamed, Selman Ozbayat, Gerardo Romo Luevano, Tim Michalka
    Qualcomm Technologies Inc.
  • P-I.12. Modeling of Mixed CNT Bundle for Sub-threshold Interconnects [143]
    Ashish Singh, Rohit Dhiman, Rajeevan Chandel
    *NIT Hamirpur
  • P-I.13. Signal Integrity Analysis on High-Density Silicon Interposer Package Technology for Next Generation Applications [174]
    Surender Singh, Ashish Gupta
    Cadence Design System Inc
  • P-I.14. A Study on Radiation characteristics of GSM Band Diversity Antenna using different types of Mobile Hand-set Casing [196]
    G. Shrikanth Reddy, Ankita Deo
    IIT Mandi

7:30 - 9:30
Gala Reception

8:30 - 9:15
Plenary Session 2
Chair:
Rakesh Malik, Vervesemi
  • M-II.1. Cognition-Driven Approach to Electromagnetic Modeling and Optimization
    Q. J. Zhang
    Carleton University

9:15 - 11:00
Session 5: Power Delivery Networks
Chairs:
Arun Chandrasekhar, Intel
Ruey-Beei Wu, NTU
  • T-I.1. Simulation Based Impedance Characterization of PDN in High Performance Multi-chip HTCC Packages for Avionics [29]
    Akash Dang+ , Shiva Prasad Jilla*, Krishan Kumar+, Gurvinder Singh +, Rohit Sharma**, Atanu Mukerji*
    *Cadence Design Systems, India,
    +Semi-Conductor Laboratory, ISRO/DOS,
    **Indian Institute of Technology Ropar
  • T-I.2. Multipin Optimization of Decoupling Capacitors on Practical Printed Circuit Structures [65]
    Ihsan Erdin*, Ram Achar+
    *Celestica LLC,
    +Carleton University
  • T-I.3. Method to Model Input Ripple Voltage in Multi-Domain Fully Integrated Voltage Regulators [103]
    Srinivasan Govindan**,*, Dipanjan Gope*, Krishna Bharath+, Srikrishnan Venkataraman**
    *Indian Institute of Science,
    +Intel,
    **Intel Technology, India PVT. LTD
  • .
  • T-I.4. Analysis of electrical power in IBM POWER9 direct-attached memory subsystem [204]
    Anil Lingambudi1, Michael Pardeik, Sharath Manujath, Wiren Becker
    IBM
  • T-I.5. A Quick Assessment of Nonlinearity in Power Delivery Networks [70]
    Vijender Kumar Sharma*, Jai Narayan Tripathi+, Hitesh Shrimali*
    *Indian Institute of Technology Mandi, India,
    +STMicroelectronics Pvt. Ltd., India

11:00 - 11:20
Tea/Coffee Break

11:20 - 12:30
Session 6 - Panel: Emerging Technologies
Chair:
Madhavan Swaminathan, Georgia Tech

Panelists:
* Ram Viswanath (Intel) - Advanced Packaging
* Q.J.Zhang (Carleton Univ.) - Machine learning applied to Design
* Taranjit Kukal (Cadence) - Chip-Package-System/EDA
* Prashanth Rao (Mathworks) - Machine learning Tool Box for Design
* Naresh Kumar (Tektronix) - Measurements/Test
* Jai Pollayil (Ansys) - Multi-physics/EDA


12:30 - 1:30
Lunch Break

1:30 - 3:00
Session 7: Poster/Interactive Session 2
Chairs:
Anil Lingambudi, IBM
Jingook Kim, UNIST
  • P-II.1. Enhancing Shielding Effectiveness of EMI Film using Fiber Type Conductive Structure [74]
    JaeHeung Ye+, Hai Au Huynh+, JungJe Bang*, Min Park*, JaeDeok Lim*, SoYoung Kim+
    *Samsung Electronics,
    +Sungkyunkwan University
  • P-II.2. Package Level Radio Frequency Interference Shielding Structure using Via Array [157]
    Hai Au Huynh, Yongbong Han, Hoang Van Nguyen, SoYoung Kim
    Sungkyunkwan University
  • P-II.3. A Shortest Path Algorithm for 3D Integrated Circuit TSV Assignment [90]
    Aman Soni, Sahil Deshmukh, Somesh Kumar
    Indian Institute of Information Technology Nagpur (IIITN), Nagpur, India
  • P-II.4. 112G PAM4/56G NRZ Interconnect Design for High Channel Count Packages [64]
    Hui Liu, Qian Ding, Jenny Jiang
    Intel Corporation
  • P-II.5. Transient and Crosstalk Analysis of Doped and Dielectric Inserted MLGNR Interconnects [192]
    Haritha Yeleti*, Mekala Girish Kumar*, Rajeevan Chandel**, Yash Agrawal
    *Vidya Jyothi Institute of Technology,
    +Dhirubhai Ambani Institute of Information and Communication Technology,
    **National Institute of Technology Hamirpur
  • P-II.6. Power Delivery Network Optimization in High-Speed BGA Package [151]
    Rohit Mishra, Zakir Husain, Ramanand Hegde
    Microsemi
  • P-II.7. Reduced Graphene Oxide Based Resistive Liquid Level Sensor [46]
    Vaishakh Kedambaimoole*, Pavithra B*, Neelotpala Kumar+, Athulya Babu**, Vijay Shirhatti*, Suresh Nuthalapati*, Manjunath Nayak*, Dinesh N S*, Konandur Rajanna*
    *Indian Institute of Science,
    +Manipal Institute of Technology,
    **National Institute of Technology
  • P-II.8. Noise Coupling Analysis from High Voltage Capacitor Discharging Circuit in an Electronic Safety and Arming Device [179]
    Hyungmin Kang, Dong-Hyun Kim, Subin Kim, Seokwoo Hong, Shinyoung Park, and Joungho Kim
    KAIST
  • P-II.9. Extension of EMPSIJ Method for Substrate Noise Induced Jitter: an Inverter Case Study [209]
    Vijender Kumar Sharma+, Jai Narayan Tripathi*, Hitesh Shrimali+
    *STMicroelectronics Pvt. Ltd.,
    India, +Indian Institute of Technology Mandi
  • P-II.10. Scalable Model Using Polynomial Fitting Technique with Kriging Interpolation [25]
    Zhao Rui , Xia Bin
    School of Electronic Information and Electrical Engineering
  • P-II.11. A novel on-chip mismatch measurement technique for Nyquist rate ADCs [107]
    Ankur Bal, Vikram Singh
    ST Microelectronics
  • P-II.12. Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects [208]
    Takshashila Pathade, Urmi Shah, Yash Agrawal, Rutu Parekh
    DAIICT

2:30 - 4:10
Session 8: Electromagnetic Radiation and Interference
Chairs:
Preet Yadav, NXP
Ram Achar, Carleton University
  • T-II.1. Crosstalk and EMI Reduction using enhanced Guard trace technique [217]
    Ranjul Balakrishnan, Shanto Alex Thomas, Sujit Sharan
    Intel
  • T-II.2. Impact of SMT Connector Pads on High Speed Serial Links [158]
    Chang-Hsien Chen, Ching-Huei Chen, Chun-Lin Liao, Bhyrav Mutnury
    DELLEMC
  • T-II.3. A meandered loop antenna-in-package with parasitic structure at 2.4 GHz [111]
    Archana S, M Bhaskar
    National Institute of Technology Tiruchirappalli
  • T-II.4. Comparison and Application of Two Approaches Extracting Equivalent Dipole Arrays of an IC from Measured Near-Field Magnitude Data [176]
    Kyungjin Kwak*, Jingook Kim*, Tae-il Bae+, Kichul Hong+, Hyungsoo Kim+
    *Ulsan National Institute of Science and Technology,
    +SK Hynix Inc.
  • T-II.5. Non-Periodic Flipped-SIR EBG for Dual-band SSN Mitigation in 2-Layer PCB [47]
    Yu-Cong Wang*, Hao-Wei Chan*, Hsin-Chan Hsieh+, Ying-Hsi Lin+, Wen-Shan Wang+, Shih-Hung Wang+, Ruey-Beei Wu*
    *Graduate Institute of Communication Engineering,
    +Realtek Semiconductor Corporation

4:10 - 5:30
Session 9: Advanced Interconnects
Chairs:
Ritabrata Bhattacharya, Cadence
Rajeevan Chandel, NIT Hamirpur
  • T-III.1. Impact of MWCNT Radii on the Performance of Nano Regime Interconnects [130]
    Amit Kumar, Brajesh Kumar Kaushik
    Indian Institute of Technology Roorkee
  • T-III.2. A Novel Stripline Inductive Compensation Technique on High speed IO Packages [76]
    Kavitha Nagarajan, Aruna Bathini, , Ling Li Ong, Anoop Karunan, Si Guan Lee
    Intel Corporation
  • T-III.3. Variability-Aware Performance Assessment of Multi-Walled Carbon Nanotube Interconnects using a Predictor-Corrector Polynomial Chaos Scheme [34]
    Sakshi Bhatnagar, Amanda Merkley, Rena Berdine, Yingheng Li, Sourajeet Roy
    Colorado State University

5:30 - 6:00
Closing Ceremony