DDR5: SI/PI Challenges and Considerations
With each generation of Double Data Rate (DDR) memory, the data rate has kept on increasing while the supply voltage kept on decreasing for improved bandwidth and efficiency. Especially, the importance of DDR memory has been highlighted with the advent of Artificial Intelligence (AI), and the need for higher performance has surged. In order to fulfill these needs, the maximum data rate of DDR5 is to reach up to 6.4 Gbps and the supply voltage to shrink down to 1.1 V, as opposed to 3.2 Gbps and 1.2 V of DDR4, respectively.
However, these changes are expected to result in drastically reduced timing and voltage margins that need to be alleviated. Firstly, in order to improve Signal Integrity (SI), a number of equalizers such as DFE and CTLE has been newly adopted in DDR5 to account for the high-frequency channel loss. Furthermore, for Power Integrity (PI), we integrated Voltage Regulator (VR) on DDR modules for the first time for the sustainment of a stable power, and also to increase the module capacity.
This tutorial will cover these novel features regarding SI and PI, along with other minor updates, which are considered to enable higher performance and improved power management of DDR5.
Sung Joo Park, Samsung
Sung Joo Park received the B.S. and M.S. degrees in electronics engineering from Sogang University, Seoul, South Korea, in 1998 and 2000, respectively, and the Ph.D. degree from the Georgia Institute of Technology, Atlanta, GA, USA, in 2016. He has been a Principal Engineer with the DRAM Development and Technology Department, Samsung Electronics Company, Ltd., Hwasung, South Korea, where he is involved in the design and development of memory systems. He holds 14 issued patents in memory modules and systems and several patents pending. His current research interests include high-speed interfaces and signal, power, and thermal integrity in the designs of 3-D ICs and systems. Dr. Park is a member of the JEDEC Solid State Technology Association, where he has been developing industry standards since 2006. He was a recipient of the JEDEC Chairman's Award in 2010, the Samsung Fellowship in 2011, and the Best Student Paper Award at the IEEE International Symposium on Electromagnetic Compatibility in 2013.