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Tutorial-3/Speaker-3

Design Space Constraint Generation Using Machine Learning for DDR4/DDR5 Memory Systems

Key objective of a design is to come up with rules for controllable parameters so that design can be within spec. In designing interconnect and buses this means specifying ranges for interconnect length, cross section, acceptable connectors, limits on xtlak etc.

There are many methods employed for this purpose; monte carlo simulations, Design of Experiments (DOE) in combination with Response Surface Modeling (RSM) etc. Sweeping is ruled out because almost always the design space is too large.

This tutorial will explore design tuning based on fast surrogate models. The computationally efficient surrogate models can be based on machine learning techniques. Surrogate models are used to characterize the design space with respect to design objectives such as eye height, width or other normalized parameters including jitter and channel operating margin(COM). The characterization will be used to progressively tune the design space

Kumar Keshavan, Cadence Design Systems

Dr. Keshavan's expertise, spanning 30 years in the EDA industry, includes circuit simulation, circuit extraction, channel simulation, and timing analysis. He was one of the founders of Velio, Inc., a pioneer in providing SerDes switching devices to the communication industry. Dr. Keshavan has been an active participant in the EIA IBIS standards organization and recently was one of the initiators of the IBIS AMI standards for serial links. At Cadence, he is responsible for AMI modeling technologies and is involved in developing Design Space Tuning and Optimization tools.