Chip to Chip Signaling in High Speed Interconnects
Signal jitter fundamentally impacts the performance of high speed chip to chip links. This tutorial will cover the basics of signal jitter, how it is generated, measured and controlled. Topics covered include (1) clock and data signaling schemes; (2) Bit Error Rate and eye diagrams; (3) Inter-symbol interference; (4) Equalization; and (5) Data coding.
Paul D. Franzon is currently a Distinguished Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and received the Alcoa Research Award in 2005. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.