EDAPS



EDAPS




EDAPS


EDAPS



EDAPS



EDAPS



EDAPS



EDAPS




EDAPS


EDAPS


EDAPS


EDAPS



EDAPS


EDAPS


EDAPS


EDAPS


EDAPS


EDAPS

EPS



Tutorial-4/Speaker-2

Power Delivery Techniques for High Performance Processors

This tutorial will give a brief overview of Power delivery techniques used on high performance processors that consume power in excess of 100W and in turn deliver best in class performance. We will start with the Moore's law trend and the industry trend on power consumption and delivery. Next would be a summary of on die power delivery solutions with specific focus on Fully Integrated Voltage Regulator (FIVR) and its benefits and implementation We will conclude with a review of the challenges ahead and the potential solutions and techniques to handle the requirements of the next generation of high performance processors in a data centric era

Arun Chandrasekhar, Intel

Arun Chandrasekhar is a Principal Engineer at Intel India working on package design for server products as well as next generation packaging tools and technologies. He teaches packaging courses at the Indian Institute of Science and NIT, Trichy for M.Tech/B.Tech students. He has published over 30 papers at international journals and conferences with 6 patents awarded/pending. He is an active IEEE member and was the co-founding and ex-chair of the EPS Bangalore chapter and the EDAPS 2014 conference. He obtained his PhD from IMEC / KU Leuven Belgium in Microsystems packaging in 2004, M.Tech from IISc Bangalore and B.E. from the College of Engg., Guindy, Chennai. He was a research intern at IBM TJ Watson Centre in 2004.