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Tutorial-1/Speaker-1
Fundamentals of Power Integrity and Jitter Analysis

With the increasing demands for lower power consumption, higher signal speeds, decreasing feature sizes, denser designs and multi-function products, power and signal integrity effects have become the dominant factors limiting the performance of modern electronic products. A robust power network is essential for reliable operation of on-chip and on-board circuits. Voltage variations may lead to reduced noise margins and may increase propagation delays. Reduced noise margins can cause false switching of gates whereas increased delays may lead to timing errors and impede the overall operating speed of the chip. These issues coupled with high-frequency effects are making the modeling, analysis and design of power distribution networks (PDNs) consisting of chip, package and printed circuit boards, extremely challenging. If not considered during the design stage, power integrity effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in low-power high-speed designs. This tutorial presents the necessary fundamentals for understanding the multidisciplinary problem of power integrity in low-power high-speed designs while placing particular emphasis on recent developments on modeling and analysis of jitter that are induced due to power supply noise, ground noise as well as data noise.

Ramachandra Achar, Carleton University

Ramachandra Achar received the B.Eng. degree in electronics engineering from Bangalore University, Bangalore, India, in 1990, the M. Eng. degree in microelectronics from the Birla Institute of Technology and Science, Pilani, India, in 1992, and the Ph.D. degree from Carleton University, Ottawa, ON, Canada, in 1998. He is currently a Professor with the Department of Electronics Engineering, Carleton University. Prior to joining Carleton University Faculty in 2000, he served in various capacities in leading research laboratories, including T. J. Watson Research Center, IBM, New York, NY, USA, in 1995, L&T Ltd., Mysore, India, in 1993, the Central Electronics Engineering Research Institute, Pilani, India, in 1992, and the Indian Institute of Science, Bangalore, India, in 1990. His current research interests include signal/power integrity analysis, circuit simulation, parallel and numerical algorithms, EMC/EMI analysis, microwave/RF algorithms, modeling/simulation methodologies for sustainable and renewable energy, and mixed-domain analysis. Dr. Achar received several prestigious awards, including Carleton University research achievement awards in 2010 and 2004, Natural Science and Engineering Research Council Doctoral Medal in 2000, the University Medal for the outstanding doctoral work in 1998, the Strategic Microelectronics Corporation Award in 1997, and the Canadian Microelectronics Corporation Award in 1996. He was a co-recipient of the best transactions paper award for IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY (IEEE T-CPMT) in 2013 and T-AdvP in 2007. He and his students have won numerous best student paper awards in international forums. He currently serves as the Chair of the Distinguished Lecturer (DL) Program of the Electromagnetic Compatibility Society and as the DL for the Electron Devices Society. Previously, he had served as the DL for the IEEE CAS Society in 2011-2012 and the IEEE EMC Society in 2015-2016. He also currently serves on the executive/steering/technical-program committees of several leading IEEE international conferences, including EPEPS, EDAPS, SPI, HPCPS, and SIPI, and in the technical committees, EDMS (TC-12 of CPMT), CAD (MTT-1), and SIPI (TC-10 of EMCS). He previously served as a Guest Editor of the IEEE TCPMT, for two special issues on "Variability Analysis" and "3D-ICs/Interconnects" in 2015 and as the General Chair for HPCPS in 2012-2015, as a General Co-Chair of NEMO in 2015, SIPI in 2016, and EPEPS in 2010 and 2011 and as an International Guest Faculty on the invitation of the Department of Information Technology of Government of India, under the SMDP-II Program in 2012. He is a Founding Faculty Member of the Canada-India Center of Excellence, Chair of the joint chapters of CAS/EDS/SSC societies of the IEEE Ottawa Section, and is a consultant for several leading industries focused on high-frequency circuits, systems, and tools. He is a practicing professional engineer of Ontario and a fellow of Engineers Institute of Canada.